CPC 5621 PDF

When the subject is focused mainly on electronic equipment classify in this group as "additional information" only, and consider main classification in the relevant field. When reinforcements are used as interface between body and cycling saddle, e. For all other crotch area reinforcements in sports trousers, e. For all other crotch area reinforcements in sports trousers e.

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Devices or arrangements for storage of digital or analogue information in which no relative movement takes place between an information storage element and a transducer; which incorporate a selecting-device for writing-in or reading-out the information into or from the store. Semiconductor devices for storage; layout or structure of memory cells or devices at the fabrication level. Examples of places where the subject matter of this place is covered when specially adapted, used for a particular purpose, or incorporated in a larger system:.

There are further main groups which are dedicated to one or more specific types of memory cell technologies. Within these, there may be specific sub-groups for aspects such as power supply or addressing which parallel the general groups.

The convention is that, where a document describes a specific aspect for a specific cell technology without indicating its use with other cell types, it should only be classified under the technology group. If it is described as applicable to two cell types then it should be classified under each cell type and in the general group.

There are no cell-type specific sub-groups for these aspects and thus they are only classified in this place. However other aspects also covered in testing documents will be classified according to the rules of the previous paragraph.

This group covers the above mentioned aspects only when they are concerned with a semiconductor memory. Furthermore, in the case where any of the above mentioned aspects are adapted to be used with a semiconductor memory of a specific type, such aspects should be classified in the relevant group covering that specific type of semiconductor device, as long as such a specific group is present.

Power supplies, reference generators or voltage pumps in general not being concerned with semiconductor memories. Circuit means for protection against loss of information in general having no connection to semiconductor memories. Geometrical lay-out of the components in integrated circuits not concerned with semiconductor memories. If documents are clearly restricted to one specific cell type or memory technology they should not be classified here but in the group of said cell technology, unless there is no group for that cell technology.

If documents mention applications to different types of cells then they can be classified here. Covering the detection of change in supply voltage, on the voltage or the ground side, in general. Covering the characteristics of the power up and power down circuits, the standby circuits and recovery circuits.

All aspects of reading and writing of data to an address memory cell in general except the addressing of the cell. Auxiliary circuits, e. Most of the current sense amplifiers current mirrors based and most of the multi stage sense amplifiers. It also contains sometimes memories with ECC circuits. Power supply arrangements for memories with random access ports synchronised on clock signal pulse trains.

Also many early solid state music players and early solid state memory cards e. Compact Flash, SDcard. Read or Write cycle during which a series of 2, 4, 8 or more external data are sequentially input to or output from the memory device.

Circuitry used for decoding a memory address selecting a row line, a bank , a block or a range of memory cells in a semiconductor memory device. Addressing schemes, architectures or methods, e. Multiport memory using "single port cells", i.

Using last in first out [LIFO] registers for processing digital data by operating upon their order. Circuitries that have an electrical effect on the rows or word lines. Decoders, circuitry which processes the address information to make a single or plural selection of word line or row line possible. However, these decoder circuits are usually not used for the electrical activation of the row or word line.

This is the task of the word line control circuits. Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down. Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.

Read-only memories programmable only once; Semi-permanent stores, e. Memories having two distinct arrays of memory elements, one with volatile memory elements and another one with non-volatile memory elements, the latter functioning as a backup memory for the volatile part of the memory.

Memories having two types of memory cells or memory elements merged to each other or otherwise combined in the same memory array. Memories using magnetic spin effect, i. Bit line control circuits, e. MRAM specific details of selecting a memory element, e. Data output circuits, e.

Data input circuits, e. Address timing or clocking circuits; Address control signal generation or management, e. Memory cell safety or protection circuits, e. Address safety or protection circuits, i. Memories using ferroelectric elements. This covers memories with capacitive elements where the insulating dielectric material between the capacitor plates is a ferroelectric material.

Details of FRAM memory elements comprising a transistor with ferroelectric material, e. Word line control circuits, e. FRAM specific details of selecting a memory element, e. Basically this group covers DRAMs - and some further types of cells needing to be periodically and frequently refreshed such gain cells.

This group and its sub groups concerns mainly DRAM cells of any type from classic one transistor-one capacitor cell types to more exotic types such single transistor cells or gain cells. All cells have in common that they require to be updated or rewritten or refreshed frequently in order to retain their data.

This is a technology or cell type specific group and only DRAMs and memories needing frequent refreshes should be classified here. Cells with three charge-transfer gates, but it also contains gain cells and other cells with access transistors combined with another charge storage transistor. All the power supply or voltage generation circuits, e. The group contains also most of the documents concerning cells with a controlled back plate and back plate voltage circuits.

For memories with random access ports synchronised on clock signal pulse trains, e. An external signal from a memory controller usually triggers the refresh, but the rest of the refresh operation is done by circuitry internal to the memory refresh address counters etc Cells usually made of three transistors in which the charge is stored in a gate electrode of a gain transistor thereby controlling the conductivity of that transistor ,.

Memories having memory cells with positive feedback or a latch, i. This group only covers the aspects of the memory device itself. Circuitry providing for power, address decoding, signal control etc. Additional aspects relating to the cell type rather than multi-state storage per se should be classified under the relevant cell technology. Digital stores in which the storage effect is based exclusively on magnetism e.

RRAM elements in which the electrical resistance change is based on an amorphous to crystalline or crystalline to amorphous transition in a phase change material. RRAM elements in which the electrical resistance change is based on a switching mechanism in metal oxides e. RRAM elements in which the electrical resistance change is based on the formation and breaking of chemical bonds.

RRAM elements in which the electrical resistance change is based on ion movement in a solid electrolyte between metal electrodes. Memories with arrangements to save information from a volatile to a nonvolatile memory when power supply is lost and to restore the information from the nonvolatile to the volatile memory when power is restored.

Sub-groups cover details of cells adapted for this purpose, classified first by volatile and then by nonvolatile storage type. Where a document only describes the presence of a nonvolatile memory to backup a volatile memory, without cell details, it should be placed in the main group. In principle, a search for such a document would need to encompass all the sub-groups as well as the main group. More detail about the type of storage elements can be added by using Indexing Codes relating to specific cell types.

In case the nonvolatile element is not covered below, classify here with an Indexing Code to specify its type. Memories wherein a sought data word for a given field characteristic part is supplied as input to the memory, which is able to search its stored data contents to determine if the supplied data word is present among said data contents. Optionally the contents of all fields of the matching word are returned. In both cases, the effect of charge storage is to modify the threshold voltage of the transistor, e.

Aso complementary-pair type cells, in which two floating gate transistors store opposite states. This group is only used if no lower sub-group is suitable - assign multiple sub-groups rather than placing here.

Especially high-voltage switches see e. EP, figures , ramp generators see e. EP, figure 4. Memories in which the stored data are permanently defined at the time of manufacturing mask ROM or which are adapted to be programmed with data one time only after manufacture PROM.

EPROMs or flash memory arrays which are wholly or partly adapted to not be erasable e. Digital stores or memories in which information is cascaded between neighbouring data storage locations in a chain under the control of at least one common clock signal.

Digital stores or memories in which information bits circulate stepwise in a closed loop or ring arrangement. Determination of programming status in electrically erasable and programmable read only memories e.

Error detection and correction in static stores integrated on a chip of data during normal operation with adding special bits of coded information in memories. Error detection or correction of the data by redundancy in hardware where the redundant component is memory or memory area. Detection of defective computer hardware by testing during stand-by operation or during idle time, e.

Test of single circuit components not integrated in memory device e. Repairing defective memory devices by using redundant spare elements; repairing defective memory devices by reconfiguring the address space this implies a reduced memory capacity compared with a non-defective device ; algorithms for effecting such repairs.

Many of these documents include lower level features related to flash memories flash. Fuse related issues; most of these documents have descriptions at transistor level, explaining how the fuse circuits are built or how they are included in the redundancy decoding elements. In this case, a master fuse can be used to decide whether a redundant line or decoder is in use. This allows to save time when programming the fuses.

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