FT232BL DATASHEET PDF

Document No. Clearance No. Future Technology. Devices International Ltd.

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Dt Sheet. FTB Data Sheet. Document No. Neither the whole nor any part of the information contained in, or the product described in this manual, may be adapted or reproduced in any material or electronic form without the prior written consent of the copyright holder. This product and its documentation are supplied on an as-is basis and no warranty as to their suitability for any particular purpose is either made or implied.

Future Technology Devices International Ltd will not accept any claim for damages howsoever arising as a result of use or failure of this product.

Your statutory rights are not affected. This product or any variant of it is not intended for use in any medical appliance, device or system in which the failure of the product might reasonably be expected to result in personal injury. This document provides preliminary information that may be subject to change without notice.

No freedom to use patents or other intellectual property rights is implied by the publication of this document. Various 3rd party drivers are also available for other operating systems - see FTDI website www. Please note that this datasheet is not for the FTBM. When interfacing with 3.

Its prime purpose is to provide the internal 3. This can be used by an external device to reset the FTB. If not required can be left unconnected, or pulled up to VCC. Output of the internal Reset Generator. This pin can also be driven by an external 6MHz clock if required. Must be tied to GND for normal operation, otherwise the device will appear to fail. Table 3. Enable Transmit Data for RS For 6MHz operation no resistor is required.

Tri-State during device reset. Tri-State during device reset, else drives out. All of the other USB device descriptors are unchanged.

This device not only adds extra functionality to its FT8UAM predecessor and reduces external component count, but also maintains a high degree of pin compatibility with the original, making it easy to upgrade or cost reduce existing designs as well as increasing the potential for using the device in new application areas.

This section summarises the enhancements of the 2nd generation device compared to its FT8UAM predecessor. The device now incorporates an internal POR function. The existing RESET pin is maintained in order to allow external logic to reset the device where required, however for many applications this pin can now simply be hard wired to VCC. In the previous devices, an external RC circuit was required to ensure that the oscillator and clock multiplier PLL frequency was stable prior to enabling the clock internal to the device.

In this mode, any residual voltage on external circuitry is bled to GND when power is removed thus ensuring that external circuitry controlled by PWREN resets reliably when power is restored Lower Suspend Current.

Programmable Receive Buffer Timeout. In the previous device, the receive buffer timeout flushed remaining data from the receive buffer at a fixed 16ms timeout. This timeout is now programmable over USB in 1ms increments from 1ms to ms, thus allowing the device to be better 10ptimized for protocols requiring faster response times from short data packets.

TXDEN timing has now been fixed to remove the external delay that was previously required for RS applications at high baud rates. TXDEN now works correctly during a transmit sendbreak condition.

Relaxed VCC Decoupling. Improved PreScaler Granularity. Bit Bang Mode. Data packets can be sent to the device and they will be sequentially sent to the interface at a rate controlled by the prescaler setting. The FPGA device would normally be un-configured i. Application notes, software and development modules for this application area will be available from FTDI and other 3rd parties. PreScaler Divide By 1 Fix. The previous device had a problem when the integer part of the divisor was set to 1.

In the 2nd generation device setting the prescaler value to 1 gives a baud rate of 2 million baud and setting it to zero gives a baud rate of 3 million baud.

Non-integer division is not supported with divisor values of 0 and 1. Less External Support Components. For circuits requiring a long reset time where the device is reset externally using a reset generator I.

This is the preferred configuration for new designs. USB 2. Note : The device would be a USB 2. This allows multiple devices to be simultaneously connected to the same PC. Please refer to the block diagram shown in Figure 2. The 3. It requires an external decoupling capacitor to be attached to the 3V3OUT regulator output pin. It also provides 3. However, external circuitry requiring 3.

USB Transceiver. The output drivers provide 3. In accordance with the USB 2. USB Protocol Engine. Dual Port TX Buffer bytes.

Dual Port RX Buffer bytes. Handshaking, where required, is handled in hardware to ensure fast response times. Baud Rate Generator. The Baud Rate Generator provides a x16 clock input to the UART from the 48MHz reference clock and consists of a 14 bit prescaler and 3 register bits which provide fine tuning of the baud rate used to divide by a whole number plus a fraction.

The Reset Generator Cell provides a reliable power-on reset to the device internal circuitry on power up. It can also be used to reset other devices. This allows a blank part to be soldered onto the PCB and programmed as part of the manufacturing and test process.

In this case, the device will not have a serial number as part of the USB descriptor. Exceeding these may cause permanent damage to the device. The value of the Ferrite Bead depends on the total current required by the circuit — a suitable range of Ferrite Beads is available from Steward www.

To meet requirement, the 1. Failure to do this may cause some USB host or hub controllers to power up erratically.

These pins have internal K pull-up resistors to VCCIO, so they will gently pull high unless driven by some external logic. In this example, a discrete 3. VCCIO is connected to the output of the 3. For USB bus powered circuits some considerations have to be taken into account when selecting the regulator: a The regulator must be capable of sustaining its output voltage with an input voltage of 4. These devices can supply up to mA current and have a quiescent current of under 1uA.

Note: It should be emphasized that the 3. In such cases, no special care need be taken to meet the USB suspend current 0. As with bus powered 3. This limit is 2. For external logic that cannot power itself down in that way, the FTB provides a simple but effective way of turning off power to external circuitry during USB suspend.

Figure 8. Alternatively, a dedicated power switch i. A suitable power switch I. Please note the following points in connection with power controlled designs — a The logic to be controlled must have its own reset circuitry so that it will automatically reset itself when power is re-applied on coming out of suspend. A high-power bus powered device must use this descriptor in the EEPROM to inform the system of its power requirements. Either connect the power switch between the output of the 3.

This makes for an economical configuration. Figure 7. These devices do not have in-built loading capacitors. If using a crystal, use a parallel cut type. If using a resonator, see the previous note on frequency accuracy. In order to check for this condition, it is necessary to pull Dout high using a 10K resistor. Most available parts are capable of this. It is recommended to select the required part and its options carefully. An important feature of these devices is the SHDN pin which can power down the device to a low quiescent current during USB suspend mode.

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